Blog
Notes from the compiler.
What we are building inside Inferno and why: the IR, the probe, the lowering decisions, and the things that turned out to be wrong.
- 2026-07-25
What it takes to make a second vendor first-class
"Also supports AMD" is cheap. Extending the hardware model instead of forking the lowering is not.
Read → - 2026-07-21
Probe the machine, don't guess it
A device ID is not a performance profile. Inferno probes the CPU, cache lines and GPU runtime before it plans anything, and will measure bandwidth and offload cost.
Read → - 2026-07-14
Why we JIT-compile the whole inference stack
Kernels are only part of your latency. The rest hides in the stack everyone treats as fixed.
Read → - 2026-07-07
Your serving loop is the other half of the model
Kernels are the part everyone already optimized. The scheduler, cache policy and HTTP layer are the part nobody compiles; Caldrix will compile them together.
Read → - 2026-06-30
One IR from H100 to your phone
How Caldrix IR will encode FlashAttention as a transformable concept instead of a CUDA artifact.
Read →
The archive grows slowly, on purpose. We post when a piece of the compiler is worth explaining in full, not on a schedule.